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| author | Nicolas Pomarede <npomarede@corp.free.fr> | 2020-09-21 12:27:11 (GMT) |
|---|---|---|
| committer | Nicolas Pomarede <npomarede@corp.free.fr> | 2020-09-21 12:27:11 (GMT) |
| commit | 872220ab26d0e8f11f018f5740a8ac96753acac7 (patch) | |
| tree | 1546211cf3e2519cb063833c606a8a974327db6f | |
| parent | 4488530492cf17e9f421557a28fbe2a6772913cf (diff) | |
| download | hatari-872220ab26d0e8f11f018f5740a8ac96753acac7.zip hatari-872220ab26d0e8f11f018f5740a8ac96753acac7.tar.gz | |
IDE memory region should only be initialized for Falcon, else it should be a bus error region
| -rw-r--r-- | src/cpu/memory.c | 26 | ||||
| -rw-r--r-- | src/cpu/memory.h | 1 |
2 files changed, 21 insertions, 6 deletions
diff --git a/src/cpu/memory.c b/src/cpu/memory.c index 213cf7d..b0d022c 100644 --- a/src/cpu/memory.c +++ b/src/cpu/memory.c @@ -1504,6 +1504,15 @@ bool memory_region_bus_error ( uaecptr addr ) { return mem_banks[bankindex(addr)] == &BusErrMem_bank; } + +/* + * Check if an address points to the IO memory region + * Returns true if it's the case + */ +bool memory_region_iomem ( uaecptr addr ) +{ + return mem_banks[bankindex(addr)] == &IOmem_bank; +} #endif @@ -1769,12 +1778,17 @@ void memory_init(uae_u32 NewSTMemSize, uae_u32 NewTTMemSize, uae_u32 NewRomMemSt IOmem_bank.start = IOmem_start; init_bank ( &IOmem_bank , IOmem_size ); - /* IDE controller memory region: */ - map_banks_ce(&IdeMem_bank, IdeMem_start >> 16, 0x1, 0, CE_MEMBANK_CHIP16, CE_MEMBANK_NOT_CACHABLE); /* IDE controller on the Falcon */ - IdeMem_bank.baseaddr = IdeMemory; - IdeMem_bank.mask = IdeMem_mask; - IdeMem_bank.start = IdeMem_start ; - init_bank ( &IdeMem_bank , IdeMem_size ); + /* IDE controller memory region at 0xF00000 (only for Falcon, else it's a bus error region) */ + if ( Config_IsMachineFalcon() ) + { + map_banks_ce(&IdeMem_bank, IdeMem_start >> 16, 0x1, 0, CE_MEMBANK_CHIP16, CE_MEMBANK_NOT_CACHABLE); /* IDE controller on the Falcon */ + IdeMem_bank.baseaddr = IdeMemory; + IdeMem_bank.mask = IdeMem_mask; + IdeMem_bank.start = IdeMem_start ; + init_bank ( &IdeMem_bank , IdeMem_size ); + } + else + map_banks_ce(&BusErrMem_bank, IdeMem_start >> 16, 0x1, 0, CE_MEMBANK_CHIP16, CE_MEMBANK_NOT_CACHABLE); /* Illegal memory regions cause a bus error on the ST: */ map_banks_ce(&BusErrMem_bank, 0xF10000 >> 16, 0x9, 0, CE_MEMBANK_CHIP16, CE_MEMBANK_NOT_CACHABLE); diff --git a/src/cpu/memory.h b/src/cpu/memory.h index db330db..c117a01 100644 --- a/src/cpu/memory.h +++ b/src/cpu/memory.h @@ -510,6 +510,7 @@ extern addrbank *get_mem_bank_real(uaecptr); #ifdef WINUAE_FOR_HATARI extern bool memory_region_bus_error ( uaecptr addr ); +extern bool memory_region_iomem ( uaecptr addr ); extern void memory_map_Standard_RAM ( Uint32 MMU_Bank0_Size , Uint32 MMU_Bank1_Size ); #endif extern void memory_init(uae_u32 NewSTMemSize, uae_u32 NewTTMemSize, uae_u32 NewRomMemStart); |