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| author | Thomas Huth <huth@tuxfamily.org> | 2022-12-07 20:32:39 (GMT) |
|---|---|---|
| committer | Thomas Huth <huth@tuxfamily.org> | 2022-12-07 20:36:16 (GMT) |
| commit | 090bfcc9af2ed94a569a0923246833c3ce0811a8 (patch) | |
| tree | fbbe6ef2b6a0b351085b176f6aa0fde9a2b062d8 | |
| parent | 82e12e1f06f15c48809ae3d822fa81718e29d905 (diff) | |
| download | hatari-090bfcc9af2ed94a.zip hatari-090bfcc9af2ed94a.tar.gz | |
Fix the CPU frequency setting of the Mega STE
Thanks to Christian Zietz for checking this on a real machine!
| -rw-r--r-- | src/ioMemTabSTE.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/ioMemTabSTE.c b/src/ioMemTabSTE.c index da1ced9..d79e68a 100644 --- a/src/ioMemTabSTE.c +++ b/src/ioMemTabSTE.c @@ -31,10 +31,10 @@ const char IoMemTabSTE_fileid[] = "Hatari ioMemTabSTE.c"; /** * Take into account Mega STe Cache/Processor Control register $ff8e21.b $FFFF8E21 Mega STe Cache/Processor Control - BIT 1 : Cache (0 - disabled, 1 - enabled) - BIT 0 : CPU Speed (0 - 8mhz, 1 - 16mhz) + BIT 0 : Cache (0 - disabled, 1 - enabled) + BIT 1 : CPU Speed (0 - 8mhz, 1 - 16mhz) - We handle only bit 0, bit 1 is ignored (cache is not emulated) + We handle only bit 1, bit 0 is ignored (cache is not emulated) */ void IoMemTabMegaSTE_CacheCpuCtrl_WriteByte(void) { @@ -44,7 +44,7 @@ void IoMemTabMegaSTE_CacheCpuCtrl_WriteByte(void) * normal MegaSTE, if the user did not request a faster one manually */ if (ConfigureParams.System.nCpuLevel == 0 && ConfigureParams.System.nCpuFreq <= 16) { - if ((busCtrl & 0x1) == 1) { + if ((busCtrl & 0x2) != 0) { /* 16 Mhz bus for 68000 */ Configuration_ChangeCpuFreq ( 16 ); } |